Hi, On Thu, Mar 10, 2022 at 7:22 AM Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx> wrote: > > From: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> > > Despite the SN65DSI86 being an eDP bridge, on some systems its output is > routed to a DisplayPort connector. Enable DisplayPort mode when the next > component in the display pipeline is detected as a DisplayPort > connector, and disable eDP features in that case. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> > Reworked to set bridge type based on the next bridge/connector. > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx> > -- > Changes since v1/RFC: > - Rebased on top of "drm/bridge: ti-sn65dsi86: switch to > devm_drm_of_get_bridge" > - eDP/DP mode determined from the next bridge connector type. > > Changes since v2: > - Remove setting of Standard DP Scrambler Seed. (It's read-only). > - Prevent setting DP_EDP_CONFIGURATION_SET in > ti_sn_bridge_atomic_enable() > - Use Doug's suggested text for disabling ASSR on DP mode. > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index c892ecba91c7..93b54fcba8ba 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -62,6 +62,7 @@ > #define SN_LN_ASSIGN_REG 0x59 > #define LN_ASSIGN_WIDTH 2 > #define SN_ENH_FRAME_REG 0x5A > +#define ASSR_CONTROL BIT(0) nit that the ASSR_CONTROL define is no longer used. Other than that, this patch looks fine to me. Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
