On Thu, 03 Mar 2022 16:26:31 +0000, Biju Das wrote: > Document the device tree binding for the Renesas RZ/G2UL Type-1 > and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1 > SoC. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > v1->v2: > * No change > --- > .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
