Fillup the ADC stub node in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 39 +++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 5d39e765c291..3ddf0f24071c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -260,8 +260,45 @@
};
adc: adc@10059000 {
+ compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg R9A07G054_ADC_PRESETN>,
+ <&cpg R9A07G054_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
};
sbc: spi@10060000 {
--
2.17.1
