Hi Miquel, On Tue, Feb 22, 2022 at 11:34 AM Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote: > The Renesas RZN1 DMA IP is a based on a DW core, with eg. an additional > dmamux register located in the system control area which can take up to > 32 requests (16 per DMA controller). Each DMA channel can be wired to > two different peripherals. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/N1 DMA mux > + > +maintainers: > + - Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > + > +allOf: > + - $ref: "dma-router.yaml#" > + > +properties: > + compatible: > + const: renesas,rzn1-dmamux Do we want an SoC-specific compatible value, too? See also my comments on the dmamux driver. > + > + '#dma-cells': > + const: 6 > + description: > + The first four cells are dedicated to the master DMA controller. The fifth > + cell gives the DMA mux bit index that must be set starting from 0. The > + sixth cell gives the binary value that must be written there, ie. 0 or 1. > + > + dma-masters: > + minItems: 1 > + maxItems: 2 > + > + dma-requests: > + const: 32 Do we need this in DT? It depends on the actual dmamux hardware, and is (currently) the register width of the CFG_DMAMUX register. The rest LGTM (I'm no dma-router expert),so with the above clarified: Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
