On Wed, Jan 19, 2022 at 3:02 PM Geert Uytterhoeven
<geert+renesas@xxxxxxxxx> wrote:
> Add initial Pin Function Controller (PFC) support for the Renesas R-Car
> S4-8 (R8A779F0) SoC.
>
> Based on a larger patch in the BSP by LUU HOAI.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
I accidentally sent out an old version, lacking changes to I2C[45]:
- Replace "PINMUX_IPSR_PHYS_NOFN(y, z)" by "PINMUX_IPSR_NOFN(GP1_x, y,
z)", as I2C requires GPSR1[x] to be configured for peripheral mode,
> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
> + /* GP1_08 = SCL4 */
> + PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0),
> + PINMUX_IPSR_PHYS_NOFN(SCL4, SEL_I2C4_3),
PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0),
PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3),
> +
> + /* GP1_09 = SDA4 */
> + PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0),
> + PINMUX_IPSR_PHYS_NOFN(SDA4, SEL_I2C4_3),
PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0),
PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3),
> +
> + /* GP1_10 = SCL5 */
> + PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0),
> + PINMUX_IPSR_PHYS_NOFN(SCL5, SEL_I2C5_3),
PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0),
PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3),
> +
> + /* GP1_11 = SDA5 */
> + PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0),
> + PINMUX_IPSR_PHYS_NOFN(SDA5, SEL_I2C5_3),
PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0),
PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3),
> --- a/drivers/pinctrl/renesas/sh_pfc.h
> +++ b/drivers/pinctrl/renesas/sh_pfc.h
> @@ -436,6 +437,16 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
> #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
> PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
>
> +/*
> + * Describe a pinmux configuration in which a pin is physically multiplexed
> + * with other pins and has no representation in a Peripheral Function Select
> + * Register (IPSR)
> + * - fn: Function name
> + * - psel: Physical multiplexing selector
> + */
> +#define PINMUX_IPSR_PHYS_NOFN(fn, psel) \
> + PINMUX_DATA(fn##_MARK, FN_##psel)
This should be dropped.
> +
> /*
> * Describe a pinmux configuration for a single-function pin with GPIO
> * capability.
I will update my topic/r8a779f0-pfc-v1 branch accordingly, and make
sure the correct version will be included in today's renesas-drivers
release.
My apologies for the trouble.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
