Hi Geert,
Thank you for the review.
On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
> > clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
> > add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> > ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
> > Nov.2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > Acked-by: Rob Herring <robh@xxxxxxxxxx>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> Before I queue this in renesas-clk-for-v5.18, I'm wondering if you
> want to add the DRP_M, DRP_D, and DRP_A core clocks, too?
>
Good point lets get everything in one shot, I'll send a v2 including
the above core clocks.
Cheers,
Prabhakar
