Hi Geert, On Fri, Jan 21, 2022 at 9:26 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Fri, Jan 21, 2022 at 2:06 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > Document the CSI-2 block which is part of CRU found in Renesas > > RZ/G2L SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- > > Hi Geert/All, > > > > vclk and pclk clocks are shared with CRU both CSI and CRU driver are using > > pm_runtime. pclk clock is necessary for register access where as vclk clock > > is only used for calculations. So would you suggest passing vclk as part of > > What do you mean by "calculations"? To set the CSI2nMCT2 register bits (FRRSKW/FRRCLK), vclk clock rate is used. > The bindings say this is the main clock? > That is because the RZG2L_clock_list_r02_02.xlsx mentions it as the main clock. > > clocks (as currently implemented) or pass the vclk clock rate as a dt property. > > Please do not specify clock rates in DT, but always pass clock > specifiers instead. > The clock subsystem handles sharing of clocks just fine. > Agreed. Cheers, Prabhakar
