Add a device node for the Pin Function Controller on the Renesas R-Car
S4-8 (R8A779F0) SoC.
Note that register banks 4-7 do not seem to be accessible as-is using
either the Control Domain (0xffd9....) or Application Domain
(0xdfd9....) addresses, so currently you cannot configure pins
controlled by these banks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
How to make the Control Domain release the bus guard, so the registers
become accessible?
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 0ac8c345558efc17..ada6ff380b203625 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -69,6 +69,14 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
+ pfc: pinctrl@e6050000 {
+ compatible = "renesas,pfc-r8a779f0";
+ reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+ <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
+ <0 0xffd90000 0 0x16c>, <0 0xffd90800 0 0x16c>,
+ <0 0xffd91000 0 0x16c>, <0 0xffd91800 0 0x16c>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
--
2.25.1
