RZ/G2L LCDC does not have DU group registers. This patch allows
accessing DU group registers for SoC's with group feature bit is
set.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 34 ++++++++++++-------------
drivers/gpu/drm/rcar-du/rcar_du_group.c | 10 +++++++-
2 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 314e865ae67e..f92636001f10 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -41,7 +41,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -69,7 +69,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -96,7 +96,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -129,7 +129,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(2) | BIT(1) | BIT(0),
.routes = {
@@ -164,7 +164,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(3) | BIT(1) | BIT(0),
.routes = {
@@ -197,7 +197,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
.features = RCAR_DU_FEATURE_CRTC_IRQ
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_VSP1_SOURCE
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -231,7 +231,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(3) | BIT(1) | BIT(0),
.routes = {
@@ -288,7 +288,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.quirks = RCAR_DU_QUIRK_ALIGN_128B,
.channels_mask = BIT(2) | BIT(1) | BIT(0),
@@ -324,7 +324,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -353,7 +353,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -378,7 +378,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -407,7 +407,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
.routes = {
@@ -446,7 +446,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(2) | BIT(1) | BIT(0),
.routes = {
@@ -481,7 +481,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(3) | BIT(1) | BIT(0),
.routes = {
@@ -516,7 +516,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(0),
.routes = {
@@ -544,7 +544,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
.features = RCAR_DU_FEATURE_CRTC_IRQ
| RCAR_DU_FEATURE_CRTC_CLOCK
| RCAR_DU_FEATURE_VSP1_SOURCE
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@@ -576,7 +576,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ
| RCAR_DU_FEATURE_VSP1_SOURCE
- | RCAR_DU_FEATURE_PLANE,
+ | RCAR_DU_FEATURE_PLANE
| RCAR_DU_FEATURE_GROUP,
.channels_mask = BIT(1) | BIT(0),
.routes = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 8665a1dd2186..3612bc9eab1b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -32,12 +32,20 @@
u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
{
+ struct rcar_du_device *rcdu = rgrp->dev;
+
+ if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_GROUP))
+ return 0;
+
return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
}
void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
{
- rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
+ struct rcar_du_device *rcdu = rgrp->dev;
+
+ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_GROUP))
+ rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
}
static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
--
2.17.1
