Hi! This adds CANFD support for V3U (R8A779A0) SoCs. The V3U's IP supports up to eight channels and has some other minor differences to the Gen3 variety: - changes to some register offsets and layouts - absence of "classic CAN" registers, both modes are handled through the CANFD register set This patch set tries to accommodate these changes in a minimally intrusive way. This revision attempts to address issues raised by reviewers to the extent possible, adds board enablement, a missing clock and some minor fixes. See below for details. It has been sucessfully tested remotely on a V3U Falcon board, but only with channels 0 and 1. We were not able to get higher channels to work in both directions yet. It is not currently clear if this is an issue with the driver, the board or the silicon, but the BSP vendor driver only works with channels 0 and 1 as well, so my bet is on one of the latter. For this reason, this series only enables known-working channels 0 and 1 on Falcon. CU Uli Changes since v1: - clk: added missing CANFD module clock - driver: fixed tests for RZ/G2L so they won't break V3U - driver: simplified two macros - DT: enabled devices 0 and 1 on Falcon board - DT: changed assigned-clock-rates to 80000000 - DT: added interrupt names Ulrich Hecht (5): clk: renesas: r8a779a0: add CANFD module clock can: rcar_canfd: Add support for r8a779a0 SoC arm64: dts: renesas: r8a779a0: Add CANFD device node arm64: dts: renesas: r8a779a0-falcon: enable CANFD 0 and 1 dt-bindings: can: renesas,rcar-canfd: Document r8a779a0 support .../bindings/net/can/renesas,rcar-canfd.yaml | 2 + .../boot/dts/renesas/r8a779a0-falcon.dts | 24 ++ arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 56 +++++ drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 + drivers/net/can/rcar/rcar_canfd.c | 231 ++++++++++++------ 5 files changed, 236 insertions(+), 78 deletions(-) -- 2.20.1
