From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L is package- and pin-compatible with the RZ/G2L. No driver changes are required as RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Acked-by: Rob Herring <robh@xxxxxxxxxx> --- v1->v2 * Included ACK from ROB --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index ef68dabcf4dc..189a0800cd1d 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven <geert+renesas@xxxxxxxxx> - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 -- 2.17.1
