Add a Yaml description for this Renesas NAND controller bindings. Provide a family-specific "rzn1" compatible and a more specific "r9a06g032" one. Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> --- .../mtd/renesas,rzn1-nand-controller.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml diff --git a/Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml new file mode 100644 index 000000000000..65d45962b5b1 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/renesas,rzn1-nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1x NAND flash controller device tree bindings + +maintainers: + - Miquel Raynal <miquel.raynal@xxxxxxxxxxx> + +allOf: + - $ref: "nand-controller.yaml" + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-nand-controller + - const: renesas,rzn1-nand-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Host controller clock + - description: External NAND bus clock + + clock-names: + items: + - const: hclk + - const: eclk + + "#address-cells": true + "#size-cells": true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: true + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + nand-controller@40102000 { + compatible = "renesas,r9a06g032-nand-controller", + "renesas,rzn1-nand-controller"; + reg = <0x40102000 0x2000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hclk_nand>, <&clk_nand>; + clock-names = "hclk", "eclk"; + #address-cells = <1>; + #size-cells = <0>; + }; -- 2.27.0
