There is no need to acquire the spinlock when reading from a pin
controller register:
1. Reading a single MMIO register is an atomic operation,
2. While sh_pfc_phys_to_virt() inside sh_pfc_read() has to traverse
all mapped windows to find the appropriate virtual address, this
does not need any locking, as the window mappings are never
changed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
To be queued in renesas-pinctrl-for-v5.17.
drivers/pinctrl/renesas/pinctrl.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index f3eecb20c0869a41..96b9de974246ac23 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -504,7 +504,6 @@ static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
unsigned int pin)
{
- unsigned long flags;
unsigned int offset;
unsigned int size;
u32 reg;
@@ -514,11 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
if (!reg)
return -EINVAL;
- spin_lock_irqsave(&pfc->lock, flags);
- val = sh_pfc_read(pfc, reg);
- spin_unlock_irqrestore(&pfc->lock, flags);
-
- val = (val >> offset) & GENMASK(size - 1, 0);
+ val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);
/* Convert the value to mA based on a full drive strength value of 24mA.
* We can make the full value configurable later if needed.
@@ -648,9 +643,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
- spin_lock_irqsave(&pfc->lock, flags);
val = sh_pfc_read(pfc, pocctrl);
- spin_unlock_irqrestore(&pfc->lock, flags);
lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
2500 : 1800;
--
2.25.1
