Hi Wolfram,
On Fri, Nov 12, 2021 at 12:56 PM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> > > + - description: IMCLK, SDHI channel main clock1.
>
> Sounds like "core"
>
> > > + - description: IMCLK2, SDHI channel main clock2. When this clock is
> > > + turned off, external SD card detection cannot be
> > > + detected.
>
> "cd"
>
> > > + - description: CLK_HS, SDHI channel High speed clock which operates
> > > + 4 times that of SDHI channel main clock1.
>
> "clkh" compared to the Gen3 bindings to me.
>
> > > + - description: ACLK, SDHI channel bus clock.
>
> This I don't understand. The CPG-MSSR clock?
RZ/G2L has more fine-grained control of module clocks.
On e.g. R-Car SoCs, there is a single "MSTP" bit to disable "the"
module clock, but in practice it may control multiple clock inputs
to a module. The actual clock tree is not documented, so we model
this as a single module clock. So probably the MSTP bit controls
both the main channel clock and the bus clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
