On 01.10.2021 9:53, Biju Das wrote:
[...]
This patch adds set_feature support for RZ/G2L.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 56
+++++++++++++++++++++++-
2 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h
b/drivers/net/ethernet/renesas/ravb.h
index d42e8ea981df..2275f27c0672 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -209,6 +209,8 @@ enum ravb_reg {
CXR56 = 0x0770, /* Documented for RZ/G2L only */
MAFCR = 0x0778,
CSR0 = 0x0800, /* Documented for RZ/G2L only */
+ CSR1 = 0x0804, /* Documented for RZ/G2L only */
+ CSR2 = 0x0808, /* Documented for RZ/G2L only */
These are the TOE regs (CSR0 included), they only exist on RZ/G2L, no?
See just one line above you can see CSR0 registers and comments on the right clearly
mentions "/* Documented for RZ/G2L only */
What I meant was commenting on them as /* RZ/GL2 only */ or some such.
Sorry for not being clear enough.
OK will do CSR0 initialisation as part of this patch instead of patch #10.
TIA!
[...]
diff --git a/drivers/net/ethernet/renesas/ravb_main.c
b/drivers/net/ethernet/renesas/ravb_main.c
index 72aea5875bc5..641ae5553b64 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
[...]
@@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device
*ndev, bool enable) static int ravb_set_features_rgeth(struct
net_device *ndev,
netdev_features_t features)
{
- /* Place holder */
+ netdev_features_t changed = features ^ ndev->features;
+ unsigned int reg;
u32 reg;
+ int error;
+
+ reg = ravb_read(ndev, CSR0);
... as this function returns u32.
I'm even suggesting to call this variable 'csr0'.
[...]
Regards,
Biju
MBR, Sergey
