On Wed, Sep 22, 2021 at 1:36 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
> 0 means clock is not supplied and 1 means clock is supplied.
> This patch fixes the issue by removing the inverted logic.
>
> Fixing the above, triggered following 2 issues
>
> 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
> Fixed this issue by adding these clocks as critical clocks.
>
> 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
> So will provide a fix in the DMA driver to turn on DMA_PCLK.
>
> Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue as a fix in renesas-clk-for-v5.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
