Hi Kieran,
Thank you for the patch.
On Thu, Sep 23, 2021 at 02:04:01AM +0100, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
>
> Provide the two MIPI DSI encoders on the V3U and connect them to the DU
> accordingly.
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
> ---
> v2
> - Fixup indentation
>
> v3
> - Fix the clock references
> - Fixup dsi1 as well
>
> arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 64 +++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index dfe99af89908..b81b2391ed29 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -1270,12 +1270,76 @@ ports {
> port@0 {
> reg = <0>;
> du_out_dsi0: endpoint {
> + remote-endpoint = <&dsi0_in>;
> };
> };
>
> port@1 {
> reg = <1>;
> du_out_dsi1: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi-encoder@fed80000 {
> + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> + reg = <0 0xfed80000 0 0x10000>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 415>,
> + <&cpg CPG_CORE R8A779A0_CLK_DSI>,
> + <&extal_clk>;
I'm not sure if EXTAL is the right clock, the datasheet isn't clear
about this. It's a guess as good as any other of the possible options,
so we could start with it and possibly fix it later, but could you try
to get clarification from Renesas on this ?
> + clock-names = "fck", "dsi", "pll";
> +
> + resets = <&cpg 415>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&du_out_dsi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi1: dsi-encoder@fed90000 {
> + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> + reg = <0 0xfed90000 0 0x10000>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 415>,
> + <&cpg CPG_CORE R8A779A0_CLK_DSI>,
> + <&extal_clk>;
> + clock-names = "fck", "dsi", "pll";
> +
> + resets = <&cpg 416>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&du_out_dsi1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi1_out: endpoint {
> };
> };
> };
--
Regards,
Laurent Pinchart
