Hi Kieran,
Thank you for the patch.
On Thu, Sep 02, 2021 at 12:53:28AM +0100, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
>
> Provide the device nodes for the DU on the V3U platforms.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
>
> ---
> v2
> - Use a single clock specification for the whole DU.
>
> arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 30 +++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index 631d520cebee..3241f7e7c01e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -1142,6 +1142,36 @@ vspd1: vsp@fea28000 {
> renesas,fcp = <&fcpvd1>;
> };
>
> + du: display@feb00000 {
> + compatible = "renesas,du-r8a779a0";
> + reg = <0 0xfeb00000 0 0x40000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 411>;
> + clock-names = "du";
With the clock name set to "du.0" as discussed in the DT bindings
review,
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 411>;
> + vsps = <&vspd0 0>, <&vspd1 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du_out_dsi0: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + du_out_dsi1: endpoint {
> + };
> + };
> + };
> + };
> +
> prr: chipid@fff00044 {
> compatible = "renesas,prr";
> reg = <0 0xfff00044 0 4>;
--
Regards,
Laurent Pinchart
