Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg: Add support
> to handle coupled clocks
>
> Hi Biju,
>
> On Fri, Aug 13, 2021 at 2:17 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > > Subject: Re: [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg: Add
> > > support to handle coupled clocks On Thu, Aug 12, 2021 at 9:00 AM
> > > Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > wrote:
> > > > > Subject: Re: [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg:
> > > > > Add support to handle coupled clocks On Tue, Jul 27, 2021 at
> > > > > 4:18 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > > > wrote:
> > > > > > The AXI and CHI clocks use the same register bit for
> > > > > > controlling clock output. Add a new clock type for coupled
> > > > > > clocks, which sets the CPG_CLKON_ETH.CLK[01]_ON bit when at
> > > > > > least one clock is enabled, and clears the bit only when both
> clocks are disabled.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > > > > Reviewed-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > @@ -333,12 +333,16 @@ rzg2l_cpg_register_core_clk(const struct
> > > > > cpg_core_clk *core,
> > > > > > * @hw: handle between common and hardware-specific interfaces
> > > > > > * @off: register offset
> > > > > > * @bit: ON/MON bit
> > > > > > + * @is_coupled: flag to indicate coupled clock
> > > > > > + * @on_cnt: ON count for coupled clocks
> > > > > > * @priv: CPG/MSTP private data
> > > > > > */
> > > > > > struct mstp_clock {
> > > > > > struct clk_hw hw;
> > > > > > u16 off;
> > > > > > u8 bit;
> > > > > > + bool is_coupled;
> > > > > > + u8 on_cnt;
> > > > >
> > > > > While u8 is probably sufficient, you may want to use unsigned
> > > > > int, as there will be a gap anyway due to alignment rules.
> > > > >
> > > > > > struct rzg2l_cpg_priv *priv; };
> > > > > >
> > > > > > @@ -392,11 +396,37 @@ static int
> > > > > > rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
> > > > > >
> > > > > > static int rzg2l_mod_clock_enable(struct clk_hw *hw) {
> > > > > > + struct mstp_clock *clock = to_mod_clock(hw);
> > > > > > + struct rzg2l_cpg_priv *priv = clock->priv;
> > > > > > + unsigned long flags;
> > > > > > +
> > > > > > + spin_lock_irqsave(&priv->rmw_lock, flags);
> > > > > > + clock->on_cnt++;
> > > > > > + if (clock->is_coupled && clock->on_cnt > 1) {
> > > > > > + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> > > > > > + return 1;
> > > > > > + }
> > > > > > +
> > > > > > + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> > > > >
> > > > > I think you can avoid taking the spinlock and touching the
> > > > > counter if the is_coupled flag is not set.
> > > >
> > > > OK.
> > > >
> > > > >
> > > > > > +
> > > > > > return rzg2l_mod_clock_endisable(hw, true); }
> > > > >
> > > > > However, I'm wondering how this can work?
> > > > >
> > > > > DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI,
> > > R9A07G044_CLK_M0,
> > > > > 0x57c, 0),
> > > > > DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI,
> > > R9A07G044_CLK_ZT,
> > > > > 0x57c, 0),
> > > > >
> > > > > This will create 2 independent clocks, each with their own
> > > > > mstp_clock structure that has the is_coupled flag set. Hence
> > > > > each clock has its own counter. Shouldn't the counter be shared?
> > > > > Am I missing something?
> > > >
> > > > Oops. You are correct. I need to add this counter to priv instead
> > > > of
> > > mstp_clocks.
> > >
> > > On second thought, a counter is overkill. A simple flag should be
> > > sufficient, as the clk core only calls .{en,dis}able() when the
> > > clock is {dis,en}enabled.
> >
> > Just to clarify, simple flag, did you mean to use bit flag? (ie, 2
> > bits , since we have 2 module clocks) when core clock calls enable, set
> a bit and reset the bit during disable.
> >
> > Then based on the 2bits, either turn on/off clock or just return the
> status.
> >
> > Please correct me, if my understanding wrong?
>
> Just one bool or bit in a bitfield, the second flag will be in the other
> struct mstp_clock (can there be three coupled clocks?).
RZ/G2L have maximum 2 coupled clocks.
>
> So I think something like below should work:
>
> struct mstp_clock {
> struct clk_hw hw;
> u16 off;
> u8 bit;
> + bool enabled;
> struct rzg2l_cpg_priv *priv;
> + struct mstp_clock *siblings;
> };
>
> .enabled needs to track the soft state of the clock.
> The actual coupling is handled through .siblings, which points to the
> other coupled clock (or forms a circular list if you can have more than
> two coupled clocks). When registering a clock, if mod->is_coupled is set,
> you walk all already registered module clocks to find one with the same
> off and bit, and link them together.
Thanks, Will prototype based on the above solution.
>
> In .{en,dis}able(), you only {en,dis}able the hardware clock if all other
> clocks in the list are disabled.
>
> if it turns out too costly to add a pointer to each clock (depends on slab
> granularity), you can also use a different struct for coupled
> clocks:
>
> struct mstp_coupled_clock {
> struct mstp_clock mstp;
> struct mstp_coupled_clock *siblings;
> };
>
> but then you do need another flag in mstp_clock to indicate it is a
> coupled clock, that can be converted to mstp_coupled_clock using
> container_of().
>
> Does that make sense?
Yes. Thanks for pointers.
Regards,
Biju
