Hi Geert,
Thank you for the review.
On Fri, Jul 16, 2021 at 9:08 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> > Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
> > sourced from P0_DIV2 referenced from HW manual Rev.0.50.
>
> OK.
>
> > Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in
> > r9a07g044-cpg.c file.
>
> I'm not so fond of adding this. Unlike the other definitions, it is
> not really part of the bindings, but merely a convenience definition
> for the driver. Furthermore it has to change when a new definition
> is ever added.
>
Agreed will drop this.
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
> > index 0728ad07ff7a..2fd20db0b2f4 100644
> > --- a/include/dt-bindings/clock/r9a07g044-cpg.h
> > +++ b/include/dt-bindings/clock/r9a07g044-cpg.h
> > @@ -30,6 +30,8 @@
> > #define R9A07G044_CLK_P2 19
> > #define R9A07G044_CLK_AT 20
> > #define R9A07G044_OSCCLK 21
> > +#define R9A07G044_CLK_P0_DIV2 22
> > +#define R9A07G044_LAST_CORE_CLK 23
>
> Third issue: off-by-one error, it should be 22 ;-)
>
23 was intentionally as these numbers aren't used for core clock count
we use r9a07g044_core_clks[] instead. Said that I'll drop this.
Cheers,
Prabhakar
> >
> > /* R9A07G044 Module Clocks */
> > #define R9A07G044_CA55_SCLK 0
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
