Re: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings

[Rob Herring <robh@xxxxxxxxxx>]

On Wed, Jun 30, 2021 at 08:30:05AM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
> 
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
>  v3:
>   * New patch.
>   * Modelled USBPHY control from phy bindings to reset bindings, since the
>     IP mainly contols the reset of USB PHY.     
> ---
>  .../reset/renesas,rzg2l-usbphy-ctrl.yaml      | 66 +++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> new file mode 100644
> index 000000000000..2a398c7ce7c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L USBPHY Control
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> +
> +description:
> +  The RZ/G2L USBPHY Control mainly controls reset and power down of the
> +  USB/PHY.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> +      - const: renesas,rzg2l-usbphy-ctrl
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  '#reset-cells':
> +    # see reset.txt in the same directory

Drop the reference. With that,

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>

> +    const: 1
> +    description: |
> +      The phandle's argument in the reset specifier is the PHY reset associated
> +      with the USB port.
> +      0 = Port 1 Phy reset
> +      1 = Port 2 Phy reset
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - power-domains
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +    phyrst: usbphy-ctrl@11c40000 {
> +        compatible = "renesas,r9a07g044-usbphy-ctrl",
> +                     "renesas,rzg2l-usbphy-ctrl";
> +        reg = <0x11c40000 0x10000>;
> +        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> +        resets = <&cpg R9A07G044_USB_PRESETN>;
> +        power-domains = <&cpg>;
> +        #reset-cells = <1>;
> +    };
> -- 
> 2.17.1
> 
>