Hi Prabhakar, On Wed, Jun 16, 2021 at 3:27 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > Add device tree binding documentation and header file for Renesas > RZ/G2L pinctrl. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L combined Pin and GPIO controller > + > +maintainers: > + - Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > + > +description: > + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO > + controller. > + Pin multiplexing and GPIO configuration is performed on a per-pin basis. > + Each port features up to 8 pins, each of them configurable for GPIO function > + (port mode) or in alternate function mode. > + Up to 8 different alternate function modes exist for each single pin. > + > +properties: > + compatible: > + enum: > + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + description: > + The first cell contains the global GPIO port index, constructed using the > + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the <dt-bindings/pinctrl/rzg2l-pinctrl.h>, for consistency with other Renesas header files? > + second cell represents consumer flag as mentioned in ../gpio/gpio.txt > + E.g. "RZG2L_GPIO(39, 1)" for P39_1. > + > + gpio-ranges: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +additionalProperties: > + anyOf: > + - type: object > + allOf: > + - $ref: pincfg-node.yaml# > + - $ref: pinmux-node.yaml# > + > + description: > + Pin controller client devices use pin configuration subnodes (children > + and grandchildren) for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + phandle: true > + function: true > + groups: true RZ/G2L uses per-pin configuration, and, unlike R-Car, the configuration registers do not have the concept of pin groups. Hence I'm wondering why you are using "function" and "group" properties, and not per-pin "pinmux" properties, like RZ/A2? > + pins: true > + bias-disable: true > + bias-pull-down: true > + bias-pull-up: true > + drive-strength: > + enum: [ 2, 4, 8, 12 ] > + power-source: > + enum: [ 1800, 2500, 3300 ] > + slew-rate: true > + gpio-hog: true > + gpios: true > + input-enable: true > + output-high: true > + output-low: true > + line-name: true > --- /dev/null > +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h include/dt-bindings/pinctrl/rzg2l-pinctrl.h, for consistency? > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings. > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + * > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H > +#define __DT_BINDINGS_PINCTRL_RZG2L_H __DT_BINDINGS_RZG2L_PINCTRL_H Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
