Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 3/7] drivers: clk: renesas: r9a07g044-cpg: Update
> {GIC,IA55,SCIF} clock entries
>
> Hi Biju,
>
> On Fri, Jun 18, 2021 at 11:58 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Update {GIC,IA55,SCIF} clock entries to CPG driver to match with
> > RZ/G2L clock list hardware manual(Rev0.2).
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -32,6 +32,7 @@ enum clk_ids {
> > CLK_PLL3_DIV2,
> > CLK_PLL3_DIV4,
> > CLK_PLL3_DIV8,
> > + CLK_PLL3_DIV16,
> > CLK_PLL4,
> > CLK_PLL5,
> > CLK_PLL5_DIV2,
> > @@ -42,6 +43,14 @@ enum clk_ids {
> > };
> >
> > /* Divider tables */
> > +static const struct clk_div_table dtable_3a[] = {
> > + {0, 1},
> > + {1, 2},
> > + {2, 4},
> > + {3, 8},
> > + {4, 32},
> > +};
>
> Divider tables have to end with a sentinel entry that has .div = 0.
> Actually the same bug is present for dtable_3b[], oops.
> Both tables are identical, perhaps they can be shared?
OK. Will fix this in next version.
Cheers,
Biju
>
> > +
> > static const struct clk_div_table dtable_3b[] = {
> > {0, 1},
> > {1, 2},
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
