Add I2C{0,1,2.3} clock entries.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 5c215b6c06e0..c7be8ede494d 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -100,6 +100,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK,
R9A07G044_CLK_P1,
0x518, BIT(1), BIT(0)),
+ DEF_MOD("i2c0", R9A07G044_I2C0_PCLK,
+ R9A07G044_CLK_P0,
+ 0x580, BIT(0), BIT(0)),
+ DEF_MOD("i2c1", R9A07G044_I2C1_PCLK,
+ R9A07G044_CLK_P0,
+ 0x580, BIT(1), BIT(1)),
+ DEF_MOD("i2c2", R9A07G044_I2C2_PCLK,
+ R9A07G044_CLK_P0,
+ 0x580, BIT(2), BIT(2)),
+ DEF_MOD("i2c3", R9A07G044_I2C3_PCLK,
+ R9A07G044_CLK_P0,
+ 0x580, BIT(3), BIT(3)),
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK,
R9A07G044_CLK_P0,
0x584, BIT(0), BIT(0)),
--
2.17.1
