Re: [PATCH 6/7] clk: renesas: rcar-gen3: Add custom clock for PLLs

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Quoting Geert Uytterhoeven (2021-03-26 05:00:59)
> +}
> +
> +static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> +                               unsigned long parent_rate)
> +{
> +       struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
> +       unsigned int mult, i;
> +       u32 val;
> +
> +       mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
> +       mult = clamp(mult, 1U, 128U);
> +
> +       val = readl(pll_clk->pllcr_reg);
> +       val &= ~CPG_PLLnCR_STC_MASK;
> +       val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
> +       writel(val, pll_clk->pllcr_reg);
> +
> +       for (i = 1000; i; i--) {
> +               if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
> +                       return 0;
> +
> +               cpu_relax();
> +       }

Why not readl_poll_timeout()?

> +
> +       return -ETIMEDOUT;
> +}
> +




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