Improve accuracy in the .determine_rate() callback for Z and Z2 clocks
by using rounded divisions. This is similar to the calculation of rates
and multipliers in the .recalc_rate() resp. set_rate() callbacks.
Sample impact for a few requested clock rates:
- R-Car H3:
- Z 500 MHz: 468 MHz => 515 MHz
- Z2 1000 MHz: 973 MHz => 1011 MHz
- R-Car M3-W:
- Z 500 MHz: 422 MHz => 516 MHz
- Z2 800 MHz: 750 MHz => 788 MHz
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index a241bf6e904f2f66..6b389c1caca76f07 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -83,10 +83,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
if (max_mult < min_mult)
return -EINVAL;
- mult = div64_ul(req->rate * 32ULL, prate);
+ mult = DIV_ROUND_CLOSEST_ULL(req->rate * 32ULL, prate);
mult = clamp(mult, min_mult, max_mult);
- req->rate = div_u64((u64)prate * mult, 32);
+ req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
return 0;
}
--
2.25.1
