On Sun, Feb 28, 2021 at 9:54 PM Sergey Shtylyov <s.shtylyov@xxxxxxxxxxxx> wrote:
> According to the RZ/A1H Group, RZ/A1M Group User's Manual: Hardware,
> Rev. 4.00, the TRSCER register has bit 9 reserved, hence we can't use
> the driver's default TRSCER mask. Add the explicit initializer for
> sh_eth_cpu_data::trscer_err_mask for R7S72100.
>
> Fixes: db893473d313 ("sh_eth: Add support for r7s72100")
> Signed-off-by: Sergey Shtylyov <s.shtylyov@xxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
