Add nodes for:
- CPU1-3, which are Cortex A15 at 1.5 GHz, living in PM domain A2SL,
- CPU4-7, which are Cortex A7 at 1.0 GHz, living in PM domain A2KL.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
arch/arm/boot/dts/r8a73a4.dtsi | 70 ++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index e5fb1ce261f72f2d..d498f848d34ab6ed 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -30,6 +30,76 @@ cpu0: cpu@0 {
next-level-cache = <&L2_CA15>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+ clock-frequency = <1500000000>;
+ power-domains = <&pd_a2sl>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+ clock-frequency = <1500000000>;
+ power-domains = <&pd_a2sl>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+ clock-frequency = <1500000000>;
+ power-domains = <&pd_a2sl>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+ clock-frequency = <1000000000>;
+ power-domains = <&pd_a2kl>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+ clock-frequency = <1000000000>;
+ power-domains = <&pd_a2kl>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+ clock-frequency = <1000000000>;
+ power-domains = <&pd_a2kl>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+ clock-frequency = <1000000000>;
+ power-domains = <&pd_a2kl>;
+ next-level-cache = <&L2_CA7>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
clocks = <&cpg_clocks R8A73A4_CLK_Z>;
--
2.25.1
