This patch adds the pinctrl device node for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@xxxxxxxx>
---
Hi!
This enables the PFC on V3U SoCs as implemented and documented in the
series "[PATCH v3 0/6] pinctrl: renesas: basic R8A779A0 (V3U) support".
CU
Uli
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index f951e6b6f696..6ac2c9d37acd 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -80,6 +80,15 @@
status = "disabled";
};
+ pfc: pin-controller@e6050000 {
+ compatible = "renesas,pfc-r8a779a0";
+ reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
+ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
+ <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
+ <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
--
2.20.1
