Add a device node for the Pin Function (PFC) instance on the Renesas
R-Car V3U (r8a779a0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
RFC because:
- The compatible value hasn't been documented yet,
- The System Group (Port Group 10) register block is missing (do we
need it?).
---
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 6bb7eaea5b246f51..0facee255237f8a5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -90,6 +90,15 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
+ pfc: pin-controller@e6050000 {
+ compatible = "renesas,pfc-r8a779a0";
+ reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
+ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
+ <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
+ <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
--
2.25.1
