Hi Kieran,
Thank you for the patch.
On Wed, Dec 16, 2020 at 05:00:18PM +0000, Kieran Bingham wrote:
> Provide VSP-X support on the V3U.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
> ---
> The FCPvX is not yet connected here, as the clock domains are unclear
> for that.
>
> The register mapping space is kept at 0x8000 for now as this is a bit of
> an unknown entity (with the IIF) so playing it safe and keeping the same
> value as the BSP (0x8000) - however with no CLU on these nodes, I expect
> the register space to be suitable to be mapped at length 0x4000.
I think so too.
> arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 36 +++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index a23b4ce2e5f4..4fb28df5cd6b 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -155,6 +155,42 @@ vspd1: vsp@fea28000 {
> renesas,fcp = <&fcpvd1>;
> };
>
> + vspx0: vsp@fedd0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfedd0000 0 0x8000>;
> + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
I'm not entirely sure about the interrupt number, as there are other
VSP-related interrupts listed in the datasheet that don't seem to
correspond to any IP core. I suppose there will be a documentation
update at some point. For now I have no reason to believe the interrupts
here are incorrect.
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> + clocks = <&cpg CPG_MOD 1028>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 1028>;
> + };
> +
> + vspx1: vsp@fedd8000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfedd8000 0 0x8000>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1029>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 1029>;
> + };
> +
> + vspx2: vsp@fede0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfede0000 0 0x8000>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1030>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 1030>;
> + };
> +
> + vspx3: vsp@fede8000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfede8000 0 0x8000>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1031>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 1031>;
> + };
> +
> prr: chipid@fff00044 {
> compatible = "renesas,prr";
> reg = <0 0xfff00044 0 4>;
--
Regards,
Laurent Pinchart
