Hi Prabhakar,
On Tue, Nov 10, 2020 at 1:56 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> driver.
>
> Add new clk type CLK_TYPE_GEN3E3_RPCSRC to register rpcsrc as a fixed
> clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
> parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
> (parent is cross verified against MD[4:1] pins) which has been set prior
> to booting the kernel.
>
> MD[4] MD[3] MD[2] MD[1]
> 0 0 0 1 -> RPCSRC CLK source is PLL1
> 0 0 1 1 -> RPCSRC CLK source is PLL1
> 0 1 0 0 -> RPCSRC CLK source is PLL1
> 1 0 1 1 -> RPCSRC CLK source is PLL1
> x x x x -> For any other values RPCSRC CLK source is PLL0
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> ---
> v2->v3
> * Implemented as a fixed clock
Sounds fine to me. If we ever need to configure this clock from Linux,
the driver can be changed.
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -427,6 +427,19 @@ static struct clk * __init cpg_sd_clk_register(const char *name,
> return clk;
> }
>
> +static bool __init cpg_rpcsrc_e3_parent_is_pll0(u32 mode)
> +{
> + unsigned int e3_rpcsrc = (mode & GENMASK(4, 1)) >> 1;
> + unsigned int pll1[] = { 0x1, 0x3, 0x4, 0xb, };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pll1); i++)
> + if (e3_rpcsrc == pll1[i])
> + return false;
Did you know gcc (version 9.3.0) generates smaller code for:
switch (e3_rpcsrc) {
case 0x1:
case 0x3:
case 0x4:
case 0xb:
return false;
default:
return true;
}
?
> @@ -696,6 +709,42 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
> cpg_rpcsrc_div_table,
> &cpg_lock);
>
> + case CLK_TYPE_GEN3E3_RPCSRC:
> + /*
> + * Register RPCSRC as fixed factor clock based on the
> + * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
> + * which has been set prior to booting the kernel.
> + */
> +
> + value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
> + if (cpg_rpcsrc_e3_parent_is_pll0(cpg_mode)) {
> + if (value != 2)
> + return ERR_PTR(-EINVAL);
> + } else {
> + if (value == 2)
> + return ERR_PTR(-EINVAL);
> + }
IMHO this cross-verification is not needed, and harmful: it prevents the
boot loader from changing the configuration, which I think is a valid
use case.
> +
> + switch (value) {
> + case 0:
> + div = 5;
> + break;
> + case 1:
> + div = 3;
> + break;
> + case 2:
> + parent = clks[core->parent >> 16];
> + if (IS_ERR(parent))
> + return ERR_CAST(parent);
> + div = 8;
R-Car D3 is very similar, but uses div = 5 instead of 8.
Perhaps this value can be retrieved from cpg_core_clk.div?
Of course, we can do that later, when D3 support is added.
> + break;
> + case 3:
> + default:
> + div = 2;
> + break;
> + }
> + break;
> +
> case CLK_TYPE_GEN3_RPC:
> return cpg_rpc_clk_register(core->name, base,
> __clk_get_name(parent), notifiers);
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
