Hi Marek,
On Sat, Sep 26, 2020 at 6:09 PM <marek.vasut@xxxxxxxxx> wrote:
> From: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
>
> The R-Car PCIe controller is capable of handling L0s/L1 link states.
> While the controller can enter and exit L0s link state, and exit L1
> link state, without any additional action from the driver, to enter
> L1 link state, the driver must complete the link state transition by
> issuing additional commands to the controller.
>
> The problem is, this transition is not atomic. The controller sets
> PMEL1RX bit in PMSR register upon reception of PM_ENTER_L1 DLLP from
> the PCIe card, but then the controller enters some sort of inbetween
> state. The driver must detect this condition and complete the link
> state transition, by setting L1IATN bit in PMCTLR and waiting for
> the link state transition to complete.
>
> If a PCIe access happens inside of this window, where the controller
> is inbetween L0 and L1 link states, the access generates a fault and
> the ARM 'imprecise external abort' handler is invoked.
>
> Just like other PCI controller drivers, here we hook the fault handler,
> perform the fixup to help the controller enter L1 link state, and then
> restart the instruction which triggered the fault. Since the controller
> is in L1 link state now, the link can exit from L1 link state to L0 and
> successfully complete the access.
>
> Note that this fixup is applicable only to Aarch32 R-Car controllers,
> the Aarch64 R-Car perform the same fixup in TFA, see TFA commit [1]
> 0969397f2 ("rcar_gen3: plat: Prevent PCIe hang during L1X config access")
> [1] https://github.com/ARM-software/arm-trusted-firmware/commit/0969397f295621aa26b3d14b76dd397d22be58bf
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
> Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
> Cc: Wolfram Sang <wsa@xxxxxxxxxxxxx>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
> ---
> V2: - Update commit message, add link to TFA repository commit
> - Handle the LPAE case as in ARM fault.c and fsr-{2,3}level.c
> - Cache clock and check whether they are enabled before register
> access
Thanks for the update!
> --- a/drivers/pci/controller/pcie-rcar-host.c
> +++ b/drivers/pci/controller/pcie-rcar-host.c
> @@ -13,6 +13,7 @@
>
> #include <linux/bitops.h>
> #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/interrupt.h>
> #include <linux/irq.h>
> @@ -42,6 +43,21 @@ struct rcar_msi {
> int irq2;
> };
>
> +#ifdef CONFIG_ARM
> +/*
> + * Here we keep a static copy of the remapped PCIe controller address.
> + * This is only used on aarch32 systems, all of which have one single
> + * PCIe controller, to provide quick access to the PCIe controller in
> + * the L1 link state fixup function, called from ARM fault handler.
the ARM fault handler
> + */
> +static void __iomem *pcie_base;
> +/*
> + * Static copy of bus clock pointer, so we can check whether the clock
> + * are enabled or not.
is
> + */
> +static struct clk *pcie_bus_clk;
> +#endif
> @@ -1050,4 +1072,47 @@ static struct platform_driver rcar_pcie_driver = {
> },
> .probe = rcar_pcie_probe,
> };
> +
> +#ifdef CONFIG_ARM
> +static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
> + unsigned int fsr, struct pt_regs *regs)
> +{
> + u32 pmsr;
> +
> + if (!pcie_base || !pcie_bus_clk || !__clk_is_enabled(pcie_bus_clk))
As __clk_is_enabled() handles a NULL pointer parameter, the second
test is not needed.
> + return 1;
> +
> + pmsr = readl(pcie_base + PMSR);
> +
> + /*
> + * Test if the PCIe controller received PM_ENTER_L1 DLLP and
> + * the PCIe controller is not in L1 link state. If true, apply
> + * fix, which will put the controller into L1 link state, from
> + * which it can return to L0s/L0 on its own.
> + */
> + if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
> + writel(L1IATN, pcie_base + PMCTLR);
> + while (!(readl(pcie_base + PMSR) & L1FAEG))
> + ;
To answer my own question from previous review cycle: this takes 7
cycles on r8a7791/koelsch.
> + writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
> + return 0;
> + }
> +
> + return 1;
> +}
> +
> +static int __init rcar_pcie_init(void)
> +{
> +#ifdef CONFIG_ARM_LPAE
> + hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
> + "asynchronous external abort");
> +#else
> + hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
> + "imprecise external abort");
> +#endif
As there can be only a single handler, this may interfere with a handler
for another platform in a multi-platform kernel.
Hence I think this should not be done unconditionally, but be moved to
the driver's .probe() callback.
> + return platform_driver_register(&rcar_pcie_driver);
> +}
> +device_initcall(rcar_pcie_init);
> +#else
> builtin_platform_driver(rcar_pcie_driver);
> +#endif
As this fixes the crash seen during s2ram with an Intel E1000E card
present and the e1000e driver loaded:
Tested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
