Hi Shimoda-san,
On Fri, Sep 11, 2020 at 9:44 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> Initial support for R-Car V3U (r8a779a0), including core, module
> clocks and register access, because register specification differs
> from R-Car Gen2/3.
>
> Inspired by patches in the BSP by LUU HOAI.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Thanks for the update!
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -85,6 +95,11 @@ static const u16 srcr[] = {
> 0x920, 0x924, 0x928, 0x92C,
> };
>
> +static const u16 srcr_for_v3u[] = {
> + 0xC00, 0xC04, 0xC08, 0xC0C, 0xC10, 0xC14, 0xC18, 0xC1C,
0x2C00 etc.?
> + 0xC20, 0xC24, 0xC28, 0xC2C, 0xC30, 0xC34, 0xC38,
> +};
> +
> /* Realtime Module Stop Control Register offsets */
> #define RMSTPCR(i) (smstpcr[i] - 0x20)
>
> @@ -98,6 +113,11 @@ static const u16 srstclr[] = {
> 0x960, 0x964, 0x968, 0x96C,
> };
>
> +static const u16 srstclr_for_v3u[] = {
> + 0xC80, 0xC84, 0xC88, 0xC8C, 0xC90, 0xC94, 0xC98, 0xC9C,
0x2C80 etc.?
> + 0xCA0, 0xCA4, 0xCA8, 0xCAC, 0xCB0, 0xCB4, 0xCB8,
> +};
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in clk-renesas-for-v5.10.
No need to resend, will fix while applying.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
