Hi Shimoda-san,
On Wed, Sep 9, 2020 at 4:53 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 12:22 AM
> > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > > Initial support for R-Car V3U (r8a779a0), including core, module
> > > clocks and register access, because register specification differs
> > > than R-Car Gen2/3.
> > > +struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
> > > + const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> > > + struct clk **clks, void __iomem *base,
> > > + struct raw_notifier_head *notifiers)
> > > +{
> >
> > > + case CLK_TYPE_R8A779A0_PLL20:
> > > + value = readl(base + CPG_PLL20CR);
> > > + mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > + break;
> > > +
> > > + case CLK_TYPE_R8A779A0_PLL21:
> > > + value = readl(base + CPG_PLL21CR);
> > > + mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > + break;
> > > +
> > > + case CLK_TYPE_R8A779A0_PLL30:
> > > + value = readl(base + CPG_PLL30CR);
> > > + mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > + break;
> > > +
> > > + case CLK_TYPE_R8A779A0_PLL31:
> > > + value = readl(base + CPG_PLL31CR);
> > > + mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > + break;
> >
> > Perhaps CLK_TYPE_R8A779A0_PLL[23][01] can share a common type, encoding
> > the register offset in cpg_core_clk.offset?
>
> I think so. If so, should I add a new macro in the r8a779a0-cpg-mssr.c to set .offset?
Indeed, a new macro similar to the existing DEF_GEN3_SD().
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
