Hi Prabhakar,
On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> Enable PCIe Controller and set PCIe bus clock frequency.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Chris Paterson <Chris.Paterson2@xxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-devel for v5.10.
One thing to double-check below.
> --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> @@ -238,6 +238,18 @@
> /* status = "okay"; */
> };
>
> +&pcie_bus_clk {
> + clock-frequency = <100000000>;
> +};
> +
> +&pciec {
> + /* SW2[6] determines which connector is activated
> + * ON = PCIe X4 (connector-J7)
> + * OFF = mini-PCIe (connector-J26)
The table on page 14 says it's the other way around.
According to the CBTL02042ABQ datasheet, PCIe_SEL = low
selects the first channel (PCIe x4), while PCIe_SEL = high selects the
second channel (mini-PCIe).
Enabling the switch ties the signal low, so the table must be wrong.
> + */
> + status = "okay";
> +};
> +
> &pfc {
> avb_pins: avb {
> groups = "avb_mdio", "avb_gmii";
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
