Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 1/2] dt-bindings: update usb-c-connector required > property > > Hi Biju, > > On Fri, Jul 17, 2020 at 10:09 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > wrote: > > > On Fri, Jul 17, 2020 at 08:34:33AM +0100, Biju Das wrote: > > > > Some boards have a single SS capable connector. Update > > > > usb-c-connector bindings to list port@1 as at least one of the required > property. > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev- > > > lad.rj@xxxxxxxxxxxxxx> > > > > --- > > > > Ref: https://patchwork.kernel.org/patch/11129567/ > > > > --- > > > > Documentation/devicetree/bindings/connector/usb-connector.yaml | > > > > 7 > > > > +++++-- > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/connector/usb-connector.yaml > > > > b/Documentation/devicetree/bindings/connector/usb-connector.yaml > > > > index 9bd52e6..41e0685 100644 > > > > --- > > > > a/Documentation/devicetree/bindings/connector/usb-connector.yaml > > > > +++ b/Documentation/devicetree/bindings/connector/usb- > > > connector.yaml > > > > @@ -139,8 +139,11 @@ properties: > > > > description: Sideband Use (SBU), present in USB-C. This describes > the > > > > alternate mode connection of which SBU is a part. > > > > > > > > - required: > > > > - - port@0 > > > > + anyOf: > > > > + - required: > > > > + - port@0 > > > > + - required: > > > > + - port@1 > > > > > > So the connector[1] doesn't have any High Speed (D+/D-) lanes? Those > > > are supposed to be present on all Type C connectors. > > > > Yes , USB-TypeC connector has USB3HS0_DP and USB3HS0_DM signals > apart > > from USB3S0_CLK_P, > > > USB3S0_CLK_M,USB3S0_RX_P,USB3S0_RX_M,USB3S0_TX_P,USB3S0_TX_M, > > USB3HS0_DP,USB3HS0_DM, USB30_PWEN and USB30_OVC. > > > > But the Connector is a SS Capable connector which supports UFP/DFP and > DRP. > > The SS lanes of the connector are tied to the HD3SS3220. > The D+/D- lanes of the connector are tied to the R-Car SoC directly. > > Perhaps modelling the C connector as a child of the HD3SS3220 is the issue? > If the C connector was a separate node, it could have port@1 point to the > HD3SS3220, and port@0 to the SoC? > That means there needs to be a different way to link the HD3SS3220 and the > on-SoC usb3_peri0. The current link between usb3_peri0 and hd3ss3220_ep > looks a bit strange to me, as the latter label points to the C connector, not to > the HD3SS3220 itself[2]. > > > > [1] : https://patchwork.kernel.org/patch/11129567/ > > [2] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ > arm64/boot/dts/renesas/r8a774c0-cat874.dts Yes as you suggested, we could remodel this as per schematic. 1) Connector-->SoC(HS line) 2) Connector --> HD3SS3220-->SoC (SS line) So the Graph will look like -------------------------------- 1) Connector --port0 (hs_ep --> usb3_hs_ep(SoC) -- port1 (ss_ep-->hd3ss3220_in_ep) 2) HD3SS320 -- port0 (hd3ss3220_in_ep --> ss_ep (connector) -- port1 (hd3ss3220_out_ep --> usb3_role_switch (SoC) 3) SoC -- port0 (usb3_hs_ep --> hs_ep (connector) -- port1 (usb3_role_switch --> hd3ss3220_out_ep I will send patch as per the above model. Please correct me if any thing wrong. Regards, Biju Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
