Hi Geert, On 06.02.2020 16:47, Geert Uytterhoeven wrote:
Hi Dirk, On Mon, Feb 3, 2020 at 8:29 AM Dirk Behme <dirk.behme@xxxxxxxxxxxx> wrote:Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the R-Car M3 (R8A7796) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxxxxx>Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Before I queue this in clk-renesas-for-v5.7: given the fuzz with the RPC driver, has this been tested successfully?
On a custom r8a7796 with 64MB Hyperflash attached I can read and write it via /dev/mtdx. Read data looks ok. Write data is byte swapped, but this is definitely a big-/little-endian driver issue. And not a clock one ;)
Best regards Dirk
