[removed CC stable] On Tue, Nov 12, 2019 at 01:48:03AM +0000, Yoshihiro Shimoda wrote: [...] > I'm sorry. I think I should not drop a sentence "because the bit 0 is > set to 1 on reset" which has the reverted patch from this version. Also, > the note seems to be difficult to understand. So, I'll rewrite this log > like below. Is it acceptable? > > --- > According to the R-Car Gen2/3 manual, Is this a publicly available manual ? If yes we provide a link, if not I will reword the sentence below. > "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before > enabling PCIETCTLR.CFINIT" because the bit 0 of MACCTLR is set to 1 on > reset. To avoid unexpected behaviors, this patch fixes it. > > Note that the SPCHG bit (bit 24) of MACCTLR register description said > "Only writing 1 is valid and writing 0 is invalid", but this "invalid" > means "ignored", not "prohibited". So, even if the driver writes > the SPCHG to 0, there is no problem. I know understand it, let me know if we can add a link to a manual (plus section/paragraph, etc.), I will rewrite the commit log accordingly. Thanks, Lorenzo > --- > > Best regards, > Yoshihiro Shimoda >
