Hello Sergei,
Cc: Geert, Shimoda-san, Marek
On Sun, Jun 10, 2018 at 09:24:13PM +0300, Sergei Shtylyov wrote:
> This PHY is still mostly undocumented -- the only documented registers
> exist on R-Car V3H (R8A77980) SoC where this PHY stays in a powered-down
> state after a reset and thus we must power it up for PCIe to work...
Indeed, this [1] PCIE PHY driver looks entirely V3H-focused and looking
at the "Table 54.5 PCIE Controller Phy Register Configuration" in Rcar3
HW User’s Manual Rev.2.00 Jul 2019, _all_ except one PCIE PHY register
(PHY_CLK_RST) exist on V3H and no other Rcar3 SoC.
So, except PHY_CLK_RST, this driver appears to be doomed to R8A77980.
Ironically, PHY_CLK_RST is exactly the register we now need to manage
to implement "Internal Reference Clock Supply" (HW man Chapter 54.3.14).
Just to avoid any surprises on our side, do you see any issues in
extending the driver to the whole R-Car3 family, even if only for the
sake of controlling the non-V3H PHY_CLK_RST register?
[1] 2ce7f2f425ef74 ("phy: Renesas R-Car gen3 PCIe PHY driver")
--
Best Regards,
Eugeniu
