On Wed, 23 Oct 2019 14:29:39 +0200, Geert Uytterhoeven wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
> M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
> Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
> preserve compatibility with the definitions for R-Car M3-W (R8A77960).
>
> Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
> are not included, as they are used as internal clock sources only, and
> never referenced from DT.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
> v2:
> - Add Reviewed-by.
> ---
> include/dt-bindings/clock/r8a77961-cpg-mssr.h | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a77961-cpg-mssr.h
>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
