Hi Geert,
Thanks for the series. One question below.
On Mon, Oct 07, 2019 at 12:23:30PM +0200, Geert Uytterhoeven wrote:
> Add initial support for the Renesas Salvator-X 2nd version development
> board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM.
>
> The memory map is as follows:
> - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff
> 0x000480000000 -> 0x004ffffffff
> - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff
>
> Based on a patch in the BSP by Takeshi Kihara
> <takeshi.kihara.df@xxxxxxxxxxx>.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 1 +
> .../boot/dts/renesas/r8a77961-salvator-xs.dts | 31 +++++++++++++++++++
> 2 files changed, 32 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
It is common practice in Renesas BSP to specify the SiP memory
split by suffixing the DTB names with '-{2,4}x{2,4}g' [1].
Has this ever been discussed on ML?
Here in particular, it would allow M3-W+ 2x4GiB Salvator-XS and
M3-W+ 2x2GiB (or any other DRAM split flavor of) Salvator-XS to
coexist in harmony, if the latter pops up at any point.
[1] (rcar-3.9.6) ls -1 arch/arm64/boot/dts/renesas/*dtb | grep 'g.dtb'
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g.dtb
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-2x2g.dtb
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-4x2g.dtb
arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dtb
--
Best Regards,
Eugeniu
