Quoting Geert Uytterhoeven (2019-08-30 06:45:07) > Hi Mike, Stephen, > > As the .round_rate() callback returns a long clock rate, it cannot > return clock rates that do not fit in signed long, but do fit in > unsigned long. The newer .determine_rate() callback does not suffer > from this limitation. In addition, .determine_rate() provides the > ability to specify a rate range. > > This patch series performs the customary preparatory cleanups, and > switches the Z (CPU) and SD clocks in the R-Car Gen2 and Gen3 clock > drivers from the .round_rate() to the .determine_rate() callback. > Note that the "div6" clock driver hasn't been converted yet, so div6 > clocks still use .round_rate(). > > Changes compared to v1[1]: > - Add preparatory arithmetic division improvements > - Split off cpg_sd_clock_calc_div() absorption and SD clock best rate > calculation, > - Use div_u64() for division by unsigned long, > > This has been tested on R-Car M2-W and various R-Car Gen3, and should > have no behavioral impact. >From what I recall the rate range code is broken but I can't remember how. Anyway, I was just curious if you ran into any issues with that code. > > To be queued in clk-renesas-for-v5.5.
