Hi Geert-san, > From: Geert Uytterhoeven, Sent: Wednesday, August 28, 2019 8:36 PM > > Hi all, > > Recent R-Car Gen3 SoCs added an External Request Mask Register to the > System Controller (SYSC). This register allows to mask external power > requests for CPU or 3DG domains, to prevent conflicts between powering > off CPU cores or the 3D Graphics Engine, and changing the state of > another power domain through SYSC, which could lead to CPG state machine > lock-ups. > > This patch series starts making use of this register. Note that the > register is optional, and that its location and contents are > SoC-specific. > > This was inspired by a patch in the BSP by Dien Pham > <dien.pham.ry@xxxxxxxxxxx>. > > Note that the issue fixed cannot happen in the upstream kernel, as > upstream has no support for graphics acceleration yet. SoCs lacking the > External Request Mask Register may need a different mitigation in the > future. > > Changes compared to v1[1]: > - Improve description of cover letter and first patch. > > Changes compared to RFC[2]: > - Rebased. > > This has been boot-tested on R-Car H3 ES1.0, H3 ES2.0, M3-W ES1.0, M3-N, > V3M, and E3 (only the last 3 have this register!), and regression-tested > on R-Car Gen2. > > This has not been tested on R-Car H3 ES3.0, M3-W ES2.0, and V3H. I also boot-tested on R-Car H3 ES3.0 and M3-W ES3.0. And I reviewed all patches, so: Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> Best regards, Yoshihiro Shimoda
