Hi Geert,
Thank you for the patch!
> From: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Sent: 21 August 2019 10:58
> Subject: [PATCH] arm64: dts: renesas: r8a774c0: Fix register range of display node
>
> Since the R8A774C0 SoC uses DU{0,1} only, the register block length
> should be 0x40000.
>
> Based on commit 06585ed38b6698bc ("arm64: dts: renesas: r8a77990: Fix
> register range of display node") for R-Car E3.
>
> Fixes: 8ed3a6b223159df3 ("arm64: dts: renesas: r8a774c0: Add display output support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 5ce1eb4596f54043..4ee885e7678886f6 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -1805,7 +1805,7 @@
>
> du: display@feb00000 {
> compatible = "renesas,du-r8a774c0";
> - reg = <0 0xfeb00000 0 0x80000>;
> + reg = <0 0xfeb00000 0 0x40000>;
> interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 724>,
> --
> 2.17.1
