Hi Geert, Sorry for the delay while I was on vacation. On Thu, Jul 04, 2019 1, Geert Uytterhoeven wrote: > To use the 64 MiB of SDRAM on the RZA2MEVB development board, SW6-4 must > be switched off, making the first Ethernet port unavailable. > Fortunately RZA2MEVB has two Ethernet ports, so this patch series makes > U-Boot fall back to using the second port instead. Thank you for the patches! > While this allows me to use TFTP, I still cannot boot my own non-XIP > Linux kernel (uImage with LOADADDR=0x0c008000), as it seems to crash in > the "blcs cache_on" in linux/arch/arm/boot/compressed/head.S. A similar > kernel boots fine on RSK+RZA1. Maybe it is because of the fact that for RZ/A1, both the RSK and GENMAI boards are using CS2 so the SDRAM was located at address 0x0800000. But the RZ/A2M EVB has SDRAM on CS3, so the address is 0x0C000000. Here was a patch that I had to do back in our linux-3.14 kernel for those that were using CS3. https://github.com/renesas-rz/rza_linux-3.14/commit/86ee3b7bc1f5 It looks like the current kernel has the same mask, and will need the same fix. https://github.com/renesas-rz/rza_linux-4.19/blob/master/arch/arm/boot/compressed/head.S#L207 Does that fix your issue? Chris
