On Fri, Jun 07, 2019 at 10:44:11AM -0700, Guenter Roeck wrote: > [Note: I updated the subject to "PATCH v3"] > > On Wed, Jun 05, 2019 at 02:04:00PM +0900, Yoshihiro Shimoda wrote: > > According to the hardware manual of R-Car Gen2 and Gen3, > > software should wait a few RLCK cycles as following: > > - Delay 2 cycles before setting watchdog counter. > > - Delay 3 cycles before disabling module clock. > > > > So, this patch adds such delays. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > > Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> > > Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx> > > Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx> Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
