According to the hardware manual of R-Car Gen2 and Gen3,
software should wait a few RLCK cycles as following:
- Delay 2 cycles before setting watchdog counter.
- Delay 3 cycles before disabling module clock.
So, this patch adds such delays.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
---
drivers/watchdog/renesas_wdt.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 565dbc1..e632b56 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -7,6 +7,7 @@
*/
#include <linux/bitops.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -70,6 +71,16 @@ static int rwdt_init_timeout(struct watchdog_device *wdev)
return 0;
}
+static void rwdt_wait(struct rwdt_priv *priv, unsigned long cycles)
+{
+ unsigned long periods, delays;
+
+ periods = DIV_ROUND_UP(priv->clk_rate, cycles);
+ delays = DIV_ROUND_UP(1000000UL, periods);
+
+ usleep_range(delays, 2 * delays);
+}
+
static int rwdt_start(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
@@ -80,6 +91,8 @@ static int rwdt_start(struct watchdog_device *wdev)
/* Stop the timer before we modify any register */
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
rwdt_write(priv, val, RWTCSRA);
+ /* Delay 2 cycles before setting watchdog counter */
+ rwdt_wait(priv, 2);
rwdt_init_timeout(wdev);
rwdt_write(priv, priv->cks, RWTCSRA);
@@ -98,6 +111,8 @@ static int rwdt_stop(struct watchdog_device *wdev)
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
rwdt_write(priv, priv->cks, RWTCSRA);
+ /* Delay 3 cycles before disabling module clock */
+ rwdt_wait(priv, 3);
pm_runtime_put(wdev->parent);
return 0;
--
2.7.4
