Hi, On Thu, May 23, 2019 at 06:29:37PM +0900, Nguyen An Hoan wrote: > From: Hoan Nguyen An <na-hoan@xxxxxxxxxxx> > > Fix setting for bit WOVFE of RWTCSRA. Keep it enable follow hardware document. Hmm, I can't find it in the docs. Which version of the documentation do you use? > - rwdt_write(priv, priv->cks, RWTCSRA); > + val |= priv->cks; > + rwdt_write(priv, val, RWTCSRA); Have you tested this successfully? According to the docs, CKS bits are all 1 by default. So, your |= operation should be a NOP and we can't select a CKS value anymore if I am not mistaken. > rwdt_write(priv, 0, RWTCSRB); > > while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) > cpu_relax(); > - > - rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); > + /* Enable interrupt and timer */ > + rwdt_write(priv, val | RWTCSRA_WOVFE | RWTCSRA_TME, RWTCSRA); What is the use of enabling an interrupt without having an interrupt handler? (And I never understood why there is an interrupt for an overflowing watchdog. We won't have time to serve it, or am I overlooking something obvious?) Kind regards, Wolfram
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