Hi Simon,
Thanks for your patch!
On Wed, May 8, 2019 at 1:56 PM Simon Horman <horms+renesas@xxxxxxxxxxxx> wrote:
> From: Dien Pham <dien.pham.ry@xxxxxxxxxxx>
>
> Setup a thermal zone driven by SoC temperature sensor.
> Create passive trip points and bind them to CPUFreq cooling
> device that supports power extension.
>
> In R-Car Gen3, IPA is supported for only one channel
> (on H3/M3/M3N board, it is channel THS3). Reason:
> Currently, IPA controls base on only CPU temperature.
> And only one thermal channel is assembled closest
> CPU cores is selected as target of IPA.
> If other channels are used, IPA controlling is not properly.
>
> The device supports 5 cooling states which can be categorised as follows:
>
> 0 & 1) boost (clocking up)
> 2) default
> 3 & 4) cooling (clocking down)
>
> Currently the thermal framework assumes that the default is the minimum,
> or in other words there is no provision for handling boost states.
> So this patch only describes the upper 3 states, default and cooling.
>
> A single cooling device is described for all A57 CPUs as this
> reflects that physically there is only one cooling device present.
>
> This patch improves on an earlier version by:
>
> * Omitting cooling-max-level and cooling-min-level properties which
> are no longer present in mainline as of v4.17
> * Removing an unused trip-point0 node sub-property from the trips
> property.
> * Using cooling-device indexes such that maximum refers to maximum cooling
> rather than the inverse.
>
> The long signed-off by chain below reflects many revisions, mainly
> internal, that this patch has been through.
>
> Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@xxxxxxxxxxx>
> Signed-off-by: Gaku Inami <gaku.inami.xw@xxxxxxxxxxxxxx>
> Signed-off-by: Hien Dang <hien.dang.eb@xxxxxxxxxxxxxxx>
> Signed-off-by: An Huynh <an.huynh.uj@xxxxxxxxxxxxxxx>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx>
> Signed-off-by: Simon Horman <simon.horman@xxxxxxxxxxxxx>
Did you intend to use this SoB value?
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -155,6 +155,7 @@
> power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> + dynamic-power-coefficient = <854>;
The dynamic-power-coefficient property is a property of the CPU,
documented in Documentation/devicetree/bindings/arm/cpus.yaml,
and not directly related to thermal zones.
Hence I think its addition should be done in a separate patch.
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -207,6 +208,8 @@
> power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + #cooling-cells = <2>;
> + dynamic-power-coefficient = <277>;
Likewise.
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
